One important application for LabVIEW FPGA is data reduction. This technique is used so applications do not have to transfer, store, and post process large amounts of raw data. With the on-board processing power of the FPGA this function creates a distribution of the data in the form of a histogram that can run in real time as the data is acquired. 

This function implements a histogram for the FPGA with up to 1024 bins. Under the hood it uses local FPGA memory block to store the counter values for each bin. In the normal mode (fill bin) the VI will take an input and and increment the counter value for the correct bin. However, the VI has multiple modes including fill bins, get bin, clear bin, and clear all bins. This download includes the Histogram IP and a project with an example program using each feature of the histogram VI. There is more detailed documentation for the VIs on the block diagrams.